Patent · US Active

Digitally compensated highly stable holdover clock generation techniques using adaptive filtering

US7692499B2 · kind B2 · utility

3Cited by

3References

9Claims

0Family size

Assignee

Integrated Device Technology, Inc. · US

Inventors

Xin Peng Liu · Beijing, CN
Liang Zhang · Shanghai, CN
Yong Wang · Shanghai, CN

Key dates

Filing date	Dec 31, 2007
Grant date	Apr 6, 2010
Priority date	—
Expiry date	Jan 1, 2028

Classification

Technology area (CPC H)Electricity
CPC primaryH03L7/235
WIPO fieldBasic communication processes
WIPO sectorElectrical engineering

Abstract

A system and method for generating a highly stable holdover clock utilizing an integrated circuit and an external OCXO is presented. The integrated circuit comprises an input reference clock receiver, a phase and frequency detector that generates an error signal between the input reference clock signal and a feedback clock signal, a data storage block that stores model parameters to predict frequency variations of the OCXO, an adaptive filtering module that includes a digital loop filter and algorithms for updating the model parameters and predicting frequency variations based on the model, a switch that enables the system to operate in normal or holdover mode, a digitally controlled oscillator, and a feedback divider.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.