Memory array on more than one die

US7692946B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Mohammed H. Taufique · Austin, US
• Derwin Jallice · Reston, US
• Donald W. McCauley · Lakeway, US
• John P. DeVale · Austin, US
• Edward A. Brekelbaum · Pflugerville, US
• Jeffrey P. Rupley, II · Round Rock, US
• Gabriel H. Loh · Bellevue, US
• Bryan Black · Austin, US

Key dates

• Filing date: Jun 29, 2007
• Grant date: Apr 6, 2010
• Expiry date: Jun 29, 2027

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2924/0002
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

For one disclosed embodiment, an apparatus may comprise a first die including a first plurality of memory cells for a memory array and a second die including a second plurality of memory cells for the memory array. The second die may include a shared line for the memory array to conduct digital signals for memory cells of both the first and second plurality of memory cells. Other embodiments are also disclosed.