Semiconductor device
US7692973B2 · kind B2 · utility
3Cited by
36References
34Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 23, 2007 |
| Grant date | Apr 6, 2010 |
| Priority date | — |
| Expiry date | Nov 25, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/01
Abstract
A semiconductor device is provided, which comprises at least a cell including a plurality of memory elements connected in series. Each of the plurality of memory elements includes a channel formation region, source and drain regions, a floating gate, and a control gate. Each of the source and drain regions is electrically connected to an erasing line through a semiconductor impurity region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.