SRAM split write control for a delay element
US7693001B2 · kind B2 · utility
3Cited by
2References
5Claims
0Family size
Assignee
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Key dates
| Filing date | Jan 14, 2008 |
| Grant date | Apr 6, 2010 |
| Priority date | — |
| Expiry date | Jan 14, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4125
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A Static Random Access Memory (SRAM) having a split write control is described. The SRAM includes bit, write, and write-word lines. Each memory cell within the SRAM includes a delay which is coupled to a dedicated write-word line. When a cell is not being written, its delay receives a delay signal on its associated write-word line, which increases the response time of the cell. When a cell is to be written, however, its delay receives a bypass signal on its associated write-word line, which decreases the response time of the SRAM cell.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.