Combined inverse fast fourier transform and guard interval processing for efficient implementation of OFDM based systems
US7693034B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 27, 2003 |
| Grant date | Apr 6, 2010 |
| Priority date | — |
| Expiry date | Oct 4, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L27/2607
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A circuit for converting frequency domain information to time domain information includes an Inverse Fast Fourier Transform circuit having a length of N coefficients. The Inverse Fast Fourier Transform circuit is adapted to receive input data of length N coefficients and generate output data of length N coefficients that are circularly shifted by m coefficients. The circuit also includes Cyclical Prefix Insertion circuit adapted to insert a cyclical prefix of length m. The Cyclical Prefix Insertion circuit includes a first switch, connected to the Inverse Fast Fourier Transform circuit, a buffer, having an input connected to the first switch and an output, the buffer having a length m, and a second switch, coupled to the first switch and to the buffer. The first and second switches selectively couple the output of the buffer and the Inverse Fast Fourier Transform circuit to an output of the second switch. The buffer is reduced to length m.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.