Nonvolatile memory with active and passive wear leveling
US7694066B2 · kind B2 · utility
4Cited by
6References
11Claims
0Family size
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Key dates
| Filing date | Nov 8, 2006 |
| Grant date | Apr 6, 2010 |
| Priority date | — |
| Expiry date | Jul 27, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/7211
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory system including a nonvolatile semiconductor storage device includes: a nonvolatile memory unit that includes a first data area in which data is frequently rewritten and a second data area in which data is hardly rewritten; and a control unit. The control unit sequentially selects logical block addresses in the second data area in which data is hardly rewritten and updates physical block addresses at new rewriting destinations in the first data area in which data is frequently rewritten to physical block addresses corresponding to the logical block addresses selected.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.