Method and apparatus for optimizing power consumption in a multiprocessor environment
US7694160B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 31, 2006 |
| Grant date | Apr 6, 2010 |
| Priority date | — |
| Expiry date | Sep 28, 2028 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for reducing net power consumption in a computer system includes identifying a plurality of processing states operable to execute a task. A processing state and current drain pattern is selected that is most power efficient. A selected processing state may include one or more processing elements of the computer system such as one or more processors or accelerators and indicates the manner in which one or more portions of the received task may be distributed among the processing elements of the computer system. The current drain pattern selected may be a constant current drain pattern or a pulsed current drain pattern and may be selected to optimize power consumption when executing the task among the one or more processing elements.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.