Method for designing semiconductor package, system for aiding to design semiconductor package, and computer program product therefor
US7694245B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 27, 2007 |
| Grant date | Apr 6, 2010 |
| Priority date | — |
| Expiry date | Sep 13, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3011
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for designing a semiconductor package is disclosed, wherein the semiconductor package comprises a semiconductor chip and an adjustment target. A first target variable is calculated in consideration of a first transition state where an output level of the semiconductor chip changes from a low level to a high level. A second target variable is calculated in consideration of a second transition state where an output level of the semiconductor chip changes from the high level to the low level. Inferior one of the first and the second target variables is selected as a main target variable. The main target variable and a predetermined constraint represented in frequency domain are compared to decide design guidelines for the adjustment target.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.