Systems and methods for providing defect-tolerant logic devices
US7696774B2 · kind B2 · utility
Inventors
Key dates
| Filing date | May 20, 2008 |
| Grant date | Apr 13, 2010 |
| Priority date | — |
| Expiry date | May 20, 2028 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/49002
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The present invention describes systems and methods to provide defect-tolerant logic devices. An exemplary embodiment of the present invention provides a defect-tolerant logic device including a plurality of CMOS gates and at least one defective CMOS gate included within the plurality of CMOS gates. Additionally, the at least one defective CMOS gate is enabled to be reconfigured into a pseudo-NMOS transistor if a P-network of the at least one defective CMOS gate is diagnosed as defective. Furthermore, the at least one defective CMOS gate is enabled to be reconfigured into a pseudo-PMOS transistor if the N-network of the at least one defective CMOS gate is diagnosed as defective.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.