Locating hardware faults in a parallel computer
US7697443B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 13, 2006 |
| Grant date | Apr 13, 2010 |
| Priority date | — |
| Expiry date | Sep 18, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L45/243
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Locating hardware faults in a parallel computer, including defining within a tree network of the parallel computer two or more sets of non-overlapping test levels of compute nodes of the network that together include all the data communications links of the network, each non-overlapping test level comprising two or more adjacent tiers of the tree; defining test cells within each non-overlapping test level, each test cell comprising a subtree of the tree including a subtree root compute node and all descendant compute nodes of the subtree root compute node within a non-overlapping test level; performing, separately on each set of non-overlapping test levels, an uplink test on all test cells in a set of non-overlapping test levels; and performing, separately from the uplink tests and separately on each set of non-overlapping test levels, a downlink test on all test cells in a set of non-overlapping test levels.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.