Programmable receiver equalization circuitry and methods
US7697600B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 14, 2005 |
| Grant date | Apr 13, 2010 |
| Priority date | — |
| Expiry date | Nov 9, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/03019
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Data signals transmitted over transmission media suffer from attenuation caused by the transmission media. Equalization circuitry may be provided to compensate for attenuation caused by the transmission media. Equalization circuitry may include multiple stages arranged in series to allow the frequency responses of the stages to aggregate together. Each stage may be programmable to insert a zero, which causes the frequency response of the stage to increase in magnitude by 20 dB/decade. The frequency location of the zero may also be programmable to allow each stage to contribute a certain amount of gain for a specific frequency. Each stage may also be programmable to determine the location of poles for reduction of high frequency noise and cross-talk cancellation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.