Patent · US Active

Methods and apparatus for equalization in high-speed backplane data communication

US7697603B1 · kind B1 · utility

11Cited by

3References

29Claims

0Family size

Assignee

Altera Corporation · US

Inventors

Shoujun Wang · Gatineau, CA
Tad Kwasniewski · Ottawa, CA
Bill Bereza · Ottawa, CA

Key dates

Filing date	Oct 18, 2004
Grant date	Apr 13, 2010
Priority date	—
Expiry date	Feb 11, 2029

Classification

Technology area (CPC H)Electricity
CPC primaryH04L25/03885
WIPO fieldDigital communication
WIPO sectorElectrical engineering

Abstract

Equalization circuitry that includes an analog equalizer and a decision feedback equalizer (DFE) is provided for high-speed backplane data communication. The analog equalizer reduces the number of taps that are required by the DFE, which lessens the error propagation of the DFE. Furthermore, the DFE includes a summing circuit and flip-flop circuitry. The flip-flop circuitry may be used as part of a phase detector by clock and data recovery circuitry. The summing circuit may further be embedded into the flip-flop circuitry to reduce the feedback path delay, thereby allowing for higher speed operation. The DFE may be extended to multiple taps by including additional flip-flops.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.