Single path architecture with digital automatic gain control for SDARS receivers
US7697911B2 · kind B2 · utility
7Cited by
0References
24Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 8, 2006 |
| Grant date | Apr 13, 2010 |
| Priority date | — |
| Expiry date | Aug 25, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04H40/90
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
An SDARS receiver includes an analog front end configured to receive a composite signal. An A/D converter is coupled to the analog front end and converts the signal to a digitized signal. A digital down converter (DDC) is coupled to the A/D converter and down converts the digitized signal to a down converted signal. A demodulator demodulates the down converted signal. The receiver includes a digital automatic gain control (DAGC) coupled to an output of the A/D converter and before the demodulator. An automatic gain controller is coupled to the DAGC for providing an automatic gain control signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.