Integrated circuit, chip stack and data processing system
US7698470B2 · kind B2 · utility
29Cited by
8References
38Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 6, 2007 |
| Grant date | Apr 13, 2010 |
| Priority date | — |
| Expiry date | Feb 19, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2224/73265
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit includes a first connection and a memory circuit. The integrated circuit is switchable between a master mode of operation, in which a buffer between the first connection and the memory circuit is activated, and a slave mode of operation, in which the buffer between the first connection and the memory circuit is deactivated.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.