System and method for reducing unnecessary cache operations
US7698508B2 · kind B2 · utility
4Cited by
8References
8Claims
0Family size
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Key dates
| Filing date | Feb 14, 2007 |
| Grant date | Apr 13, 2010 |
| Priority date | — |
| Expiry date | Mar 8, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0817
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method for cache management in a data processing system. The data processing system includes a processor and a memory hierarchy. The memory hierarchy includes at least an upper memory cache, at least a lower memory cache, and a write-back data structure. In response to replacing data from the upper memory cache, the upper memory cache examines the write-back data structure to determine whether or not the data is present in the lower memory cache. If the data is present in the lower memory cache, the data is replaced in the upper memory cache without casting out the data to the lower memory cache.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.