Dynamic hardware multithreading and partitioned hardware multithreading
US7698540B2 · kind B2 · utility
26Cited by
13References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 31, 2006 |
| Grant date | Apr 13, 2010 |
| Priority date | — |
| Expiry date | May 1, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/485
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In an embodiment of the invention, a method for dynamic hardware multithreading, includes: using a hardware halt function or a hardware yield function in a processor core in order to enable or disable a hardware thread that shares the core; wherein the hardware thread is disabled by placing the hardware thread in a halt state or yield state, and allowing another hardware thread to utilize the core.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.