Automatic halting of a processor in debug mode due to reset
US7698544B2 · kind B2 · utility
4Cited by
6References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 14, 2006 |
| Grant date | Apr 13, 2010 |
| Priority date | — |
| Expiry date | Sep 16, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/24
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed herein is a system and method of operating a processor before and after a reset has been asserted. Prior to a reset being asserted the processor operates in one of a plurality of states wherein primary code may be executed by the processor depending on said state. Upon a reset being asserted the processor begins executing code for a reset routine. The processor also executes a process such that the processor operates in the same state it was in prior to the reset upon the reset no longer being asserted.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.