Method for radiation tolerance by logic book folding
US7698681B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 14, 2007 |
| Grant date | Apr 13, 2010 |
| Priority date | — |
| Expiry date | Mar 17, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/00338
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A logic book for a programmable device such as an application-specific integrated circuit (ASIC) achieves improved radiation tolerance by providing transistors of the same doping type in different well regions that are physically isolated by intervening well regions with complementary doping. For example, n-type field effect transistors (NFETs) may be located in two outer rows of the book with separate Pwell regions, while p-type transistors are located in two inner rows of the book sharing a common Nwell region. Since the NFETs in separate wells are physically isolated from each other, a circuit structure which uses two NFETs in the two outer rows is much less likely to suffer multiple upsets from a single radiation strike. More complicated embodiments of the present invention include additional transistor rows in the stack with isolated Nwells and Pwells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.