Transistor, memory cell, memory cell array and method of forming a memory cell array

US7700983B2 · kind B2 · utility

Assignee

• Qimonda AG · DE

Inventors

• Martin Popp · Dresden, DE
• Juergen Faul · Radebeul, DE
• Thomas Schuster · Ottenbach, DE
• Jens Hahn · Dresden, DE

Key dates

• Filing date: Dec 15, 2005
• Grant date: Apr 20, 2010
• Expiry date: Dec 15, 2025

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/62

Abstract

One embodiment of the present invention relates to a transistor that is at least partially formed in a semiconductor substrate having a surface. In particular, the transistor includes a first source/drain region, a second source/drain region, a channel region connecting said first and second source/drain regions. Said channel region is disposed in said semiconductor substrate. A channel direction is defined by a line connecting said first and said second source/drain regions. A gate groove is formed in said semiconductor substrate. Said gate groove is formed adjacent to said channel region. Said gate groove includes an upper portion and a lower portion, said upper portion being adjacent to said lower portion, and a gate dielectric layer disposed between said channel region and said gate groove. The lower portion of said gate groove is filled with polysilicon whereas the upper portion of said gate groove is filled with a metal or a metal compound thereby forming a gate electrode disposed along said channel region. Said gate electrode controls an electrical current flowing between said first and second source/drain regions.