Method and apparatus to align and standardize packet based parallel interfaces
US7701977B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 10, 2008 |
| Grant date | Apr 20, 2010 |
| Priority date | — |
| Expiry date | Oct 1, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L1/0061
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A packet alignment system for pre-processing/aligning incoming packets may comprise one or more registers for receiving control signals and data signals. An aligner may cyclically shift said data signals to form a plurality of shifted data words. A plurality of pipe registers may collect and generate an adjusted control signal for each one of the plurality of shifted data words. A filtering logic may identify one of the plurality of shifted data words as a desired aligned data word. The filter logic may also be configured for registering header data, payload data and ECRC data contained in the desired aligned data word in a header register, a payload register and an ECRC register, respectively. An output interface may generate an outgoing signal and provide data from at least one of the header register, the payload register and the ECRC register.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.