Simultaneous bidirectional differential signalling interface
US7702004B2 · kind B2 · utility
Inventors
Key dates
| Filing date | Dec 9, 2003 |
| Grant date | Apr 20, 2010 |
| Priority date | — |
| Expiry date | Sep 4, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/085
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
Bidirectional differential point to point simultaneous high speed signalling is provided between integrated circuits with highly effective echo canceling. Each integrated circuit comprises a transmitter for transmitting a first signal to another integrated circuit and a receiver for receiving a second signal from the other integrated circuit. The transmitter has an output buffer; a receiver has a receiver buffer and is co-located on the same integrated circuit; and a differential buffer is coupled between the input of the transmitter buffer and the output of the receiver buffer. To increase the quality of receiving the second signal, a third signal adjusted in phase and amplitude is coupled at the output of the receive buffer, so that the echoing of the first signal is canceled. Preferably, the rise time of the third signal is also adjusted.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.