Jitter reduction circuit and frequency synthesizer
US7702292B2 · kind B2 · utility
3Cited by
5References
10Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Nov 10, 2005 |
| Grant date | Apr 20, 2010 |
| Priority date | — |
| Expiry date | Jan 27, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/1565
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The jitter reduction circuit to reduce phase noise in a pulse train, comprises: —a resettable integrator (70) to integrate the pulse train, —a comparator (72) to compare the integrated pulse train with a reference level and to generate a modified pulse train with reduced phase noise, —a crossing time interval detector (94) configured to determine a discrete time interval during which the integrated pulse train crosses the reference level and to reset the integrator between two discrete time intervals determined consecutively.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.