Optimizing cached access to stack storage
US7702855B2 · kind B2 · utility
2Cited by
3References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 11, 2005 |
| Grant date | Apr 20, 2010 |
| Priority date | — |
| Expiry date | Mar 21, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/30134
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processing device employs a stack memory in a region of an external memory. The processing device has a stack pointer register to store a current top address for the stack memory. One of several techniques is used to determine which portion or portions of the external memory correspond to the stack region. A more efficient memory policy is implemented, whereby pushes to the stack do not have to read data from the external memory in to a cache, and whereby pops from the stack do not cause stale stack data to be written back from the cache to the external memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.