TAP time division multiplexing with scan test
US7702974B2 · kind B2 · utility
7Cited by
13References
20Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Dec 17, 2004 |
| Grant date | Apr 20, 2010 |
| Priority date | — |
| Expiry date | Feb 14, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318536
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
An integrated circuit comprising (i) a plurality of portions, each portion including test control circuitry; and (ii) at least one test input arranged to receive test signals, the circuit having a test mode in which one or more of the plurality of portions are testable, wherein the circuit has a reset mode which has priority over the test mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.