Printed organic logic circuits using a floating gate transistor as a load device
US7704786B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 26, 2007 |
| Grant date | Apr 27, 2010 |
| Priority date | — |
| Expiry date | Jul 5, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10K85/113
Abstract
A method of forming an organic inverter includes providing a first metal layer having a first portion for coupling a source of a first OFET to a first power supply voltage, a second portion for coupling a drain of the first OFET to an output terminal and to a source of a second OFET, and a third portion for coupling a drain of the second OFET to a second power supply voltage, providing a semiconductor layer for overlapping a portion of the first and second first metal layer portions to form a first OFET active area, and for overlapping a portion of the second and third metal layer portions to form a second OFET active area, providing a dielectric layer for overlapping the active area and isolates the first metal layer and semiconductor layer from the second metal layer, and providing a second metal layer for overlapping the active area of the first OFET to form a gate of the first OFET and an input terminal, and for overlapping the active area of the second OFET to form a floating gate for the second OFET.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.