Delay locked loop circuit
US7705645B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 19, 2008 |
| Grant date | Apr 27, 2010 |
| Priority date | — |
| Expiry date | Mar 29, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0895
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A delay element generates a delayed clock signal which transitions with a delay from a rising (or falling) of a reference clock signal by a delay amount determined based on an output of a loop filter. A signal generation circuit generates two signals which complementarily change according to rising and falling of the reference clock signal and a transition of the delayed clock signal. A charge pump circuit performs on the loop filter, according to these two signals, a push (or pull) operation during an interval extending from a rising (or falling) of the reference clock signal to the transition of the delayed clock signal and a pull (or push) operation during an interval extending from the transition of the delayed clock signal to a falling (or rising) of the reference clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.