Duty cycle correction circuit with small duty error and wide frequency range
US7705649B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 3, 2008 |
| Grant date | Apr 27, 2010 |
| Priority date | — |
| Expiry date | Apr 3, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2005/00208
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A duty cycle correction circuit (10) for receiving an input clock signal (11) and generating an output clock signal (13) having a predetermined duty cycle includes a clock trigger circuit (12) generating the output clock signal (13) having a first clock edge triggered from the input clock signal and a second clock edge triggered from a delayed clock signal (22); a charge pump circuit (14) receiving the output clock signal and generating charging and discharging currents for a capacitor (C1) where a control voltage develops on the capacitor indicative of the duty cycle error of the output clock signal; a self-track bias circuit (18) receiving the control voltage and generating first and second bias voltages (23, 24) in response to the control voltage; and a delay-locked loop circuit (20) receiving the output clock signal and the first and second bias voltages and generating the delayed clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.