SSPC technology incorporated with thermal memory effects to achieve the fuse curve coordination
US7706116B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 22, 2007 |
| Grant date | Apr 27, 2010 |
| Priority date | — |
| Expiry date | Aug 27, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH02H6/00
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
Methods and apparatuses implement a thermal memory effect for a solid state power controller. A solid state power controller trip apparatus with thermal memory according to one embodiment comprises: a trip module including a first capacitor (156) and a counter (174), wherein the first capacitor (156) charges multiple times, when an over current event occurs, and the counter (174) accumulates a count related to the charging of the first capacitor (156) for the multiple times, to detect a trip condition; and a discharging module connected to the trip module, the discharging module including a resistor (166) and a second capacitor (158), wherein an electrical parameter associated with the count decays with time using the resistor (166) and the second capacitor (158).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.