DMA controller executing multiple transactions at non-contiguous system locations
US7707324B1 · kind B1 · utility
1Cited by
1References
16Claims
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Key dates
| Filing date | Jun 19, 2007 |
| Grant date | Apr 27, 2010 |
| Priority date | — |
| Expiry date | Nov 8, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/28
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A direct memory access controller comprises a plurality of registers defining parameters for multiple direct memory access transactions and transfer control circuitry responsive to data in the plurality of registers. The transfer control circuitry is adapted to automatically execute multiple, consecutive data transactions using the parameters of the plurality of registers. At least two consecutive data transactions are executed with respect to non-contiguous system locations.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.