Method and system for safe and efficient chip power down drawing minimal current when a device is not enabled
US7707435B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Nov 8, 2005 |
| Grant date | Apr 27, 2010 |
| Priority date | — |
| Expiry date | Jul 1, 2027 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Certain embodiments of a method and system for safe and efficient power down and drawing minimal current when a device is not enabled may comprise receiving within a network adapter chip (NAC) a signal that indicates a reduced power mode. Based on this signal, the NAC may control an off-chip voltage source that provides reduced voltage to circuitry within the NAC. The off-chip voltage source, which may comprise a first PNP transistor and a second PNP transistor, may reduce a voltage to a first voltage and a second voltage. The NAC may also reduce current through the off-chip voltage source to approximately zero amperes and an output voltage of the off-chip voltage source to approximately zero volts. The first voltage and/or the second voltage may be fed back to control the output voltage and current of the off-chip voltage source.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.