Systems and methods for low power multi-rate data paths
US7707449B2 · kind B2 · utility
1Cited by
6References
20Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Mar 29, 2006 |
| Grant date | Apr 27, 2010 |
| Priority date | — |
| Expiry date | Dec 20, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/356104
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Various systems and methods for low power multi-rate data paths are disclosed. As one example, a semiconductor device that includes a multi-rate data path is discussed. The multi-rate data path includes at least two register circuits with an output of one of the register circuits electrically coupled to an input of the other register circuit via a combinational logic block. In addition, the semiconductor device includes a control circuit that is operable to modify the rate at which the multi-rate data path operates by selectably bypassing at least one of the register circuits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.