Failure simulation based on system level boundary scan architecture
US7707470B2 · kind B2 · utility
3Cited by
3References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 26, 2006 |
| Grant date | Apr 27, 2010 |
| Priority date | — |
| Expiry date | Nov 15, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L43/50
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for reducing cost for the backplane and system test and for speeding up the time to market of a new product are disclosed. A failure simulation based on system level Boundary Scan architecture allows the use of an already available test infrastructure for test and validation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.