Checksum calculation
US7707477B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 29, 2005 |
| Grant date | Apr 27, 2010 |
| Priority date | — |
| Expiry date | Nov 10, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1004
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
In one embodiment, a checksum generator comprises an N-bit accumulator and a plurality of N-bit 3:2 carry save adders. A first plurality of the plurality of N-bit 3:2 carry save adders are coupled to receive N-bit inputs extracted from an input to the checksum generator, and one of the first plurality has an N-bit input coupled to the output of the accumulator. A second plurality of the plurality of N-bit 3:2 carry save adders have inputs coupled to outputs of the first plurality, and a most significant bit of each carry output of the first plurality is inserted as a least significant bit of the carry output at the input to the second plurality.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.