System and method for efficient uncorrectable error detection in flash memory
US7707481B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 16, 2006 |
| Grant date | Apr 27, 2010 |
| Priority date | — |
| Expiry date | Feb 23, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1012
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method for efficient uncorrectable error detection in flash memory is described. A microcontroller including a non-volatile flash memory utilizes an Error Correction Code (ECC) having a certain error detection and correction bit strength. The user data is first processed by a hash function and hash data is stored with the user data. Then, the user data and hash data are processed by the ECC system. In detection, the hash ensures that a relatively low bit-strength ECC system did not incorrectly manipulate the user data. Such a hash integrity check provides an efficient, robust detection of incorrectly corrected user data resulting from errors beyond the correction but strength of the ECC system utilized.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.