Auto-routing small jog eliminator
US7707522B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 14, 2007 |
| Grant date | Apr 27, 2010 |
| Priority date | — |
| Expiry date | Apr 24, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/394
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a method of routing a wire to a shape in an integrated circuit for minimizing undesirable jog creation during a masking process, a plurality of possible placements of the wire relative to a selected edge of the shape resulting in the wire being connected to the shape are determined. A cost is assigned to each placement, the cost indicating an amount of jog that would be created in the masking process corresponding to the placement, wherein a greater cost indicates that a greater jog would be created in the masking process than would be created by a placement assigned a lesser cost. A placement having a lowest cost of the plurality of possible placements is selected.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.