Process for fabricating a field-effect transistor with self-aligned gates

US7709332B2 · kind B2 · utility

Assignee

• COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES · FR

Inventors

• Christophe Licitra · Grenoble, FR
• Bernard Previtali · Grenoble, FR

Key dates

• Filing date: Mar 26, 2007
• Grant date: May 4, 2010
• Expiry date: Mar 26, 2027

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D86/0214

Abstract

A first gate, formed on a substrate, is surmounted by a hard layer designed, with first spacers surrounding the first gate, to act as etching mask to bound the channel and a pad that bounds a space subsequently used to form a gate cavity. The hard layer is preferably made of silicon nitride. Before flipping and bonding, a bounding layer, preferably made of amorphous silicon or polysilicon, is formed to bound drain and source areas. After flipping and bonding of the assembly on a second substrate, a second gate is formed in the gate cavity. At least partial silicidation of the bounding layer is then performed before the metal source and drain electrodes are produced.