Integrated circuit with dielectric layer
US7709359B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 5, 2007 |
| Grant date | May 4, 2010 |
| Priority date | — |
| Expiry date | Sep 5, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/60
Abstract
A method of fabricating an integrated circuit with a dielectric layer on a substrate is disclosed. One embodiment provides forming the dielectric layer in an amorphous state on the substrate, the dielectric layer having a crystallization temperature; a doping the dielectric layer; a forming of a covering layer on the dielectric layer at a temperature being equal to or below the crystallization temperature; and a heating of the dielectric layer to a temperature being equal to or greater than the crystallization temperature.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.