Multistage dual logic level voltage translator
US7710152B1 · kind B1 · utility
10Cited by
5References
27Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 6, 2007 |
| Grant date | May 4, 2010 |
| Priority date | — |
| Expiry date | Jul 6, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/356113
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A multistage dual logic level voltage translator for translating both high and low input logic levels to higher levels, at least one of which levels is above the maximum recommended voltage of transistors implementing the stages, includes an input stage for receiving input logic levels and an output stage including a high voltage converter having at least a pair of cross-coupled converter transistors responsive to the input stage and including a pair of clamping circuit connected one across each of the converter transistors, for providing the shifted low and high output logic levels.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.