Dynamic dual output latch
US7710155B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 20, 2007 |
| Grant date | May 4, 2010 |
| Priority date | — |
| Expiry date | Apr 20, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/0963
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A dynamic latch includes a first stage for receiving an input data value and for providing true and complement logic values representing the input data value; a second stage for receiving the true and complement logic values into first and second dynamic node, when a control signal is active; and a holding that outputs the true and complement logic values while the control signal is active. The second stage may provide a feedback signal to the first stage to block propagation of changes in the input data value after the true and complement logic values have been received. The feedback signal may be derived, for example, from logic values on the dynamic nodes. A holding circuit may be provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.