Digital low frequency detector
US7710161B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Jan 13, 2009 |
| Grant date | May 4, 2010 |
| Priority date | — |
| Expiry date | Jan 13, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2221/2101
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A digital circuit is disclosed for detecting clock activity in an integrated circuit (IC) device. In one implementation, a clock detection circuit can include two flip flops. A first flip flop detects activity on the clock being tested (e.g., the flip flop is set when a positive clock edge is detected). A second flip flop is coupled to the output of first flip flop and is operable by an enable signal to sample the output of the first flip flop. The output of the second flip flop is asserted as active, when a positive clock edge occurs between the release of the reset signal on the first flip flop and the assertion of the enable signal on the second flip flop. In some implementations, one or more additional flips can be interposed between the first and second flips to control metastability.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.