Averaging circuit apparatus, error signal generation system and method of averaging an error signal
US7710186B2 · kind B2 · utility
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6References
12Claims
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Key dates
| Filing date | Jun 19, 2006 |
| Grant date | May 4, 2010 |
| Priority date | — |
| Expiry date | Feb 16, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/03006
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
An averaging circuit apparatus comprises a rectifier having an input for receiving a high-speed error signal having, for example, a data rate of 10 Gbps. An integrator is coupled to the rectifier and has an error output for providing an averaged representation of the error signal. The averaged representation of the error signal is supplied to a Digital Signal Processor in a channel equalizer loop for equalizing a fiber-optic channel. The Digital Signal Processor executes an algorithm that sets tap coefficients of an analogue filter in response to the averaged representation of the error signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.