System including an inter-chip communication system
US7710329B2 · kind B2 · utility
15Cited by
0References
21Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Nov 26, 2007 |
| Grant date | May 4, 2010 |
| Priority date | — |
| Expiry date | Jun 19, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/19104
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A system including an inter-chip communication system is disclosed. One embodiment includes a base chip including a base chip transceiver network. At least one chip is stacked on the base chip, the at least one stacked chip including a substrate, a cavity formed in the substrate, a first surface, and a stacked chip transceiver network disposed on the first surface adjacent to the cavity.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.