Method of managing a multilevel memory device and related device
US7710772B2 · kind B2 · utility
Inventors
Key dates
| Filing date | Apr 25, 2008 |
| Grant date | May 4, 2010 |
| Priority date | — |
| Expiry date | Sep 1, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1006
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory has an array of k-level cells, organized into pages of words, each storing a string of bits. The memory device includes a coding circuit input with strings of N bits, and generates corresponding k-level strings. A program circuit is input with the k-level strings to stores in groups of c cells with k levels. A read circuit reads data stored in groups of c cells with k levels and generates k-level strings. A read decoding circuit is input with k-level strings read from groups of c cells with k levels to generate strings of N bits. The words of each page are grouped in groups of words, each word including groups of c cells with k levels, and at least one remaining bit of the word being stored, with corresponding remaining bits of other words of the page, in a group of c cells with k levels.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.