Method of erasing an EEPROM device
US7710787B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 11, 2006 |
| Grant date | May 4, 2010 |
| Priority date | — |
| Expiry date | Apr 11, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/3477
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for erasing an EEPROM cell which reduces the need for monitoring algorithms. The potential at the erase gate is initially raised and the potential at the control gate is lowered to cause FN tunneling through the erase gate. A subsequent soft programming step is employed to raise the potential at the control gate to a value sufficient to cause FN tunneling to start though the oxide of the transistor. A new memory device structure suitable for practicing this method employs a transistor having a floating gate, where a data value is stored as charged on the floating gate; a control gate; a control gate capacitor coupling the control gate to the floating gate; an erase gate; an erase gate capacitor coupling the erase gate to the floating gate; and an erase control circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.