Frequency synchronization
US7711078B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 1, 2007 |
| Grant date | May 4, 2010 |
| Priority date | — |
| Expiry date | Dec 1, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/181
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Systems and methods related to digital frequency locked looping to synchronize frequencies between the local signal from a local oscillator and a reference clock signal from a remote oscillator. A reference counter increments its count for every pulse in the reference clock signal. The value in the reference counter is compared to a configurable reference value. Whenever a match between the reference counter value and the reference value occurs, a hit signal is generated and the reference counter value is reinitialized. Concurrent with the above, a feedback counter increments for every pulse from the local signal. When the hit signal is generated, the value in the feedback counter is compared to a configurable feedback value (by subtraction) to generate a difference value. The difference value is then converted to a frequency adjust signal for use in either increasing or decreasing the frequency of the local oscillator. The hit signal also reinitializes the feedback counter.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.