Trap-based mechanism for tracking accesses of logical components
US7711937B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 17, 2005 |
| Grant date | May 4, 2010 |
| Priority date | — |
| Expiry date | Jun 14, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/656
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A trap-based mechanism is provided for gaining greater visibility into the memory usage of a process. To detect and record the memory accesses of a process, a virtual address range (or a plurality of address ranges) of the process is set to a protected status. This address range represents the range of virtual addresses that are to be monitored for access. By setting the address range to a protected status, whenever a memory access (in one implementation, whenever a memory write) is made to a virtual address within that address range, a trap arises. When the trap arises, a trap handler is invoked. When invoked, the trap handler records the virtual address that was accessed. In this manner, the access of the virtual address is detected and recorded without having to add extensive instrumentation code to the process.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.