Systems and methods for error reduction associated with information transfer
US7712008B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 26, 2006 |
| Grant date | May 4, 2010 |
| Priority date | — |
| Expiry date | Feb 8, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/1515
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Various systems and methods for error reduction in a digital information system are disclosed herein. As one example, a digital storage system is provided that includes a soft output Viterbi algorithm channel detector operable to receive an encoded data set, and to provide a hard and a soft output representing the encoded data set. The hard and the soft output from the soft output Viterbi algorithm channel detector are provided to a single parity row decoder that provides another hard output that is an error reduced representation of the encoded data set. The encoded data set is additionally provided from the buffer to another channel detector via a delay element. The hard output from the single parity row decoder and the time shifted encoded data set are provided to coincident with each other to another channel detector.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.