Designing integrated circuits for yield
US7712055B2 · kind B2 · utility
4Cited by
3References
21Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 29, 2007 |
| Grant date | May 4, 2010 |
| Priority date | — |
| Expiry date | Apr 18, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2111/08
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Method and system for designing integrated circuits for yield are described. Integrated circuits are designed for yield by finding worst yield corners based on design, statistical, and environmental variables and optimizing the design in light of the worst yield corners found.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.