Method and apparatus for facilitating effective and efficient optimization of short-path timing constraints
US7712067B1 · kind B1 · utility
14Cited by
7References
32Claims
0Family size
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Key dates
| Filing date | Jul 19, 2007 |
| Grant date | May 4, 2010 |
| Priority date | — |
| Expiry date | Mar 8, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/34
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for connecting a first and second component in a logic device is disclosed. A path is generated between the first and second components with an appropriate amount of delay to satisfy short-path timing constraints that define a minimum delay on the path. A first interconnect line from a plurality of interconnect lines and a second interconnect line to connect with the first interconnect line sub-optimally from a delay minimization perspective are selected in order to satisfy the short-path timing constraints.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.