Semiconductor memory device and manufacturing method thereof

US7714388B2 · kind B2 · utility

Assignee

• Kabushiki Kaisha Toshiba · JP

Inventor

• Hiroomi Nakajima · Yokohama, JP

Key dates

• Filing date: Nov 28, 2006
• Grant date: May 11, 2010
• Expiry date: Apr 16, 2027

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/62

Abstract

This discloser concerns a semiconductor device including an insulation layer; a FIN-type semiconductor layer provided on the insulation layer and including a floating body region in an electrically floating state and including a source region and a drain region at both sides of the floating body region; gate insulation films provided on both side surfaces of the floating body region; gate electrodes provided on both side surfaces of the floating body region via the gate insulation films; and a source electrode and a drain electrode respectively contacting with the upper surface of the source region and the drain region, wherein in the cross section of the FIN-type semiconductor layer in parallel with the surface of the insulation layer, a thickness of the FIN-type semiconductor layer in the floating body region is smaller than a thickness of the FIN-type semiconductor layer in the source and the drain regions.